Luento 3: Digitaalilogiikka Luento 3. u binary: AND ( ) A B = AB. u unary: NOT ( _ ) A. u precedence: NOT, AND, OR.

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1 Luento 3 Digital logic Stallings: Appendix B Combinational Circuits Simplification Sequential Circuits Luento 3-1 Luento 3-2 George Boole u ideas 1854 Claude Shannon u apply to circuit design, 1938 u father of information theory Topics: (piirisuunnittelu) Describe digital circuitry function u programming language Optimise given circuitry u use algebra (Boolean algebra) to manipulate (Boolean) expressions into simpler expressions Variables: A, B, C Values: TRUE (1), FALSE () Basic logical operations: u binary: AND ( ) A B = AB OR ( + ) B + C u unary: NOT ( _ ) A Composite operations, equations u precedence: NOT, AND, OR u parenthesis ja, tai, ei tulo, yhteenlasku, negaatio D = A+ B C = A + (( B) C) Luento 3-3 Luento 3-4 Postulates and Identities Other operations u NAND u NOR A NAND B = NOT ( A AND B) = AB A NOR B = NOT( A ORB) = A+ B How can I manipulate expressions u Simple set of rules Truth tables u What is the result of the operation (Sta6 Table B.1) Luento 3-5 (Sta6 Table B.2) Luento 3-6 / 26 / Teemu Kerola 1

2 Gates (veräjät / portit) Functionally Complete Set funktionaalisesti täydellinen joukko Implement basic Boolean algebra operations Fundamental building blocks u 1 or 3 inputs, 1 output Combine to build more complex circuits u memory, adder, multiplier, yhteenlaskupiiri, Gate delay kertolaskupiiri u change inputs, after gate delay new output available u 1 ns 1 ns.1 ns applets/cmos/cmosdemo.html (extra material) Sta6 Fig B.1 Luento 3-7 Can build all basic gates (AND, OR, NOT) from a smaller set of gates u With AND, NOT u With OR, NOT u With NAND alone u With NOR alone A + B = A B Luento 3-8 OR Sta6 Fig B.2, B.3 Combinational Circuits yhdistelmäpiirit Describing the Circuit Interconnected set of gates u m inputs, n outputs u change inputs, wait for gate delays, new outputs Each output u depends on combination of input signals u can be expressed as Boolean function of inputs Boolean equations Truth table F = ABC + ABC + ABC < inputs > <- output -> Function can be described in three ways u with Boolean equations (one equation for each output) u with truth table u with graphical symbols for gates and wires Graphical symbols Sta6 Fig B.4 (Sta6 Table B.3) Luento 3-9 Luento 3-1 Simplify Presentation (and Implementation) Boolean equations u Sum of products form (SOP) Sta6 Table B.3 Sta6 Fig B.4 Simplification Piirin yksinkertaistaminen u Product of sums form (POS) F = ( A + B + C) ( A + B + C) ( A + B + C) ( A + B + ( A + B + Which presentation is better F = ABC + ABC + ABC u Fewer gates Smaller area on chip u Smaller circuit delay Faster Boolean algebra Sta6 Fig B.5 Luento 3-11 Luento 3-12 / 26 / Teemu Kerola 2

3 Algebraic Simplification Circuits become too large to handle Use basic identities to simplify Boolean expressions May be difficult to do How to do it automatically Build a program to do it best F = ABC + ABC + ABC = AB + BC = B( A + C) Sta6 Fig B.4 Sta6 Fig B.6 f = abcd + abcd + abcd + abcd + abcd + abcd + abcd + abcd Karnaugh Map Represent Boolean function (i.e., circuit) truth table in another way u Use canonical form: each term has each variable once u Use SOP presentation Karnaugh map squares u Each square is one product (input value combination) u Value is one (1) iff the product is present o/w value is empty (Sta6 Fig B.7) Luento 3-13 Luento 3-14 Karnaugh Map Karnaugh Map Simplification u Adjacent squares differ only in one input value (wrap around) u Square for input combination = 11 (Sta6 Fig B.7) order!! If adjacent squares have value 1, input values differ only in one variable Value of that variable is irrelevant (when all other input variables are fixed for those squares) Can ignore that variable for those expressions u ignore C Luento 3-15 Luento 3-16 Using Karnaugh Maps to Minimize Boolean Functions (8) Original function Canonical form (already OK) Karnaugh Map Find smallest number of circles, each with largest number (2 i ) of 1 s ab can wrap-around Select parameter combinations corresponding to the circles Get reduced function f = abcd + abcd + abcd + abcd + abcd + abcd + abcd + abcd f = bd + ac + ab cd ac bd ab Impossible Input Variable Combinations What if some input combinations can never occur u Mark them don t care, d u treat them as or 1, whichever is best for you u more room to optimize ab d cd d d 1 1 Treat as 1 Treat as f = bd + a Luento 3-17 Luento 3-18 / 26 / Teemu Kerola 3

4 Example: Circuit to add 1 (mod 1) to 4-bit BCD decimal number (3) Example cont.: Truth Table 5 = = 6 9 = 11 = A B C D W X Y Z Truth table Karnaugh maps for W, X, Y and Z Luento 3-19 (Sta6 Table B.4) Luento 3-2 Example cont: Karnaugh Map Other Methods to simplify Boolean expressions Why u Karnaugh maps become complex with 6 input variables uine-mckluskey method u Tabular method u Automatically suitable for programming Luque Method u Based on dividing circle in different ways u Can be fractally expanded to infinitely many variables (Sta6 Fig B.1) Interesting, but not part of this course Details skipped Luento 3-21 Luento 3-22 Basic Combinatorial Circuits Building blocks for more complex circuits u Multiplexer u Encoders/decoder u Read-Only-Memory u Adder Multiplexers Select one of many possible inputs to output u black box Sta6 Fig B.12 u truth table u implementation Sta6 Table B.7 Sta6 Fig B.13 Each input/output line can be many parallel lines u select one of three 16 bit values C..15, IR..15, ALU..15 u simple extension to one line selection lots of wires, plenty of gates Sta6 Fig B.14 Luento 3-23 Luento 3-24 / 26 / Teemu Kerola 4

5 Encoders/Decoders Only one of many Encoder input or Decoder output lines can be 1 Encode that line number as output u hopefully less pins (wires) needed this way u optimise for space, not for time u Example: encode 8 input wires with 3 output pins route 3 wires around the board decode 3 wires back to 8 wires at target Sta6 Fig B.15 Read-Only-Memory (ROM) (5) Given input values, get output value u Like multiplexer, but with fixed data Consider input as address, output as contents of memory location Example u Truth tables for a ROM Sta6 Table B.8 64 bit ROM 16 words, each 4 bits wide Mem (7) = 4 Mem (11) = 14 Encode Decode u Implementation with decoder & or gates Sta6 Fig B.2 Luento 3-25 Luento 3-26 Adders A=1 1-bit adder B= Carry= Sum=1 Carry=1 1-bit adder with carry A=1 B= Carry=1 Sum= Sequential Circuits sarjalliset piirit Implementation Sta6 Table B.9, Fig B.22 Build a 4-bit adder from four 1-bit adders Sta6 Fig B.21 u Flip-Flop u S-R Latch u Registers u Counters Luento 3-27 Luento 3-28 Sequential Circuit (sarjallinen piiri) Circuit has (modifiable) internal state u remembers its previous state Output of circuit depends (also) on internal state u not only from current inputs u output = f o (input, state) u new state = f s (input, state) Circuits needed for u processor control u registers u memory Flip-Flop (kiikku) 2 states for ( or 1, true or false) 2 outputs u complement values u both always available on different pins Need to be able to change the state () Luento 3-29 Luento 3-3 / 26 / Teemu Kerola 5

6 S-R Flip-Flop or S-R Latch S-R Latch Stable States (4) Usually both R= S= 1 bit memory (value = value of ) bi-stable, when R=S= u = u =1 S = SET = Write 1 = set S=1 for a short time R = RESET = Write = set R=1 for a short time nor (, ) = 1 nor (, 1) = nor (1, ) = nor (1, 1) = R S nor nor (, ) = 1 nor (, 1) = nor (1, ) = nor (1, 1) = u output = f o (input, state), u state = f s (input, state) R: S: nor(,1)= nor(,)=1 nor(,)=1 nor(1,)= = =1 1 Luento 3-31 Luento 3-32 S-R Latch Set (=1) and Reset (=) (17) Clocked Flip-Flops Write 1: S= 1 R= R nor(,)=1 = =1 State change can happen only when clock is 1 u more control on state changes Write : R= 1 nor (, ) = 1 nor (, 1) = nor (1, ) = nor (1, 1) = S= S=1 S= S 1 nor(,1)= nor(1,1)= nor(1,)= nor(1,1)= R= R=1 R= =1 = S= S 1 nor(,)=1 Clocked S-R Flip-Flop D Flip-Flop u only one input D D = 1 and CLOCK write 1 D = and CLOCK write J-K Flip-Flop Sta6 Fig B.27 Sta6 Fig B.28 u Toggle when J=K=1 Sta6 Fig B.26 Sta6 Fig B.29 Luento 3-33 Luento 3-34 Registers Parallel registers u read/write u CPU user registers u additional internal registers Shift Registers u shifts data 1 bit to the right u serial to parallel u ALU ops u rotate Sta6 Fig B.3 (Sta6 Fig B.31) Luento 3-35 Counters Add 1 to stored counter value Counter u parallel register plus increment circuits Ripple counter (aalto, viive) u asynchronous u increment least significant bit, and handle carry bit as far as needed Synchronous counter u modify all counter flip-flops simultaneously u faster, more complex, more expensive Sta6 Fig B.32 ( Luento 3-36 / 26 / Teemu Kerola 6

7 Summary -- End of Appendix B: Digital Logic -- Gates Circuits u can implement all with NANDs or NORs u simplify circuits: Karnaugh, (uine-mckluskey, Luque, ) Simple processor Components for CPU design u ROM, adder u multiplexer, encoder/decoder u flip-flop, register, shift register, counter Luento 3-37 Luento 3-38 Kertauskysymyksiä DeMorganin laki Miten boolen funktio minimoidaan Karnaugh kartan avulla Mitä eroa sarjallisessa piirissä on verrattuna normaaliin kombinatoriseen piiriin Miten S-R kiikku toimii Luento 3-39 / 26 / Teemu Kerola 7