AUTO3030 Digitaalitekniikan jatkokurssi, harjoitus 5, ratkaisuja s2009 Tehtävien ratkaisussa käytän yhteistä top-level -suunnitteluyksikköä, jonka komponentilla toteutetaan erilaiset piirin topologiat. Top-level on: -- Janne Koljonen -- University of Vaasa -- 12.11.2009 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; -- Top-level entity: change the architecture of the component in the for...use clause. entity Tablesum is generic(bits : Natural := 4); port( reset, clock : in std_logic; x0: in std_logic_vector(bits-1 downto 0); x1: in std_logic_vector(bits-1 downto 0); x2: in std_logic_vector(bits-1 downto 0); x3: in std_logic_vector(bits-1 downto 0); x4: in std_logic_vector(bits-1 downto 0); x5: in std_logic_vector(bits-1 downto 0); y0: out std_logic_vector(bits-1 downto 0); y1: out std_logic_vector(bits-1 downto 0); y2: out std_logic_vector(bits-1 downto 0); y3: out std_logic_vector(bits-1 downto 0); y4: out std_logic_vector(bits-1 downto 0); y5: out std_logic_vector(bits-1 downto 0) ); end Tablesum; architecture arch of Tablesum is component Tablesum2 is generic(bits : Natural); port( reset, clock : in std_logic; x0: in std_logic_vector(bits-1 downto 0); x1: in std_logic_vector(bits-1 downto 0); x2: in std_logic_vector(bits-1 downto 0); x3: in std_logic_vector(bits-1 downto 0); x4: in std_logic_vector(bits-1 downto 0); x5: in std_logic_vector(bits-1 downto 0); y0: out std_logic_vector(bits-1 downto 0); y1: out std_logic_vector(bits-1 downto 0); y2: out std_logic_vector(bits-1 downto 0); jako@uwasa.fi 1
y3: out std_logic_vector(bits-1 downto 0); y4: out std_logic_vector(bits-1 downto 0); y5: out std_logic_vector(bits-1 downto 0) ); end component; for u1: Tablesum2 use entity Work.Tablesum2(arch4); u1: Tablesum2 generic map(bits) port map(reset, clock, x0, x1, x2, x3, x4, x5, y0, y1, y2, y3, y4, y5); end arch; ja komponentin entity: library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; -- Component entity with different architectures entity Tablesum2 is generic(bits : Natural); port( reset, clock : in std_logic; x0: in std_logic_vector(bits-1 downto 0); x1: in std_logic_vector(bits-1 downto 0); x2: in std_logic_vector(bits-1 downto 0); x3: in std_logic_vector(bits-1 downto 0); x4: in std_logic_vector(bits-1 downto 0); x5: in std_logic_vector(bits-1 downto 0); y0: out std_logic_vector(bits-1 downto 0); y1: out std_logic_vector(bits-1 downto 0); y2: out std_logic_vector(bits-1 downto 0); y3: out std_logic_vector(bits-1 downto 0); y4: out std_logic_vector(bits-1 downto 0); y5: out std_logic_vector(bits-1 downto 0) ); end Tablesum2; 1. Data path, pipelining, synkroninen logiikka Oletetaan, että pitää laskea 5-paikkaisen syötevektorin x summia seuraavasti: n y n = x i, jossa n = {0, 1,, 5} ja x i on b-bittinen luku. i= 0 Tee VHDL-kuvaus piiristä, joka laskee summat seuraavasti: y 0 = x 0, y 1 = y 0 + x 1, jne. Kellota piiri siten, että summan ulostuloissa on D-kiikut. -- Pipeline: kiikku ulostulossa. architecture arch1 of Tablesum2 is jako@uwasa.fi 2
y0 <= (others => '0'); y1 <= (others => '0'); y2 <= (others => '0'); y3 <= (others => '0'); y4 <= (others => '0'); y5 <= (others => '0'); y0 <= x0; y1 <= x0 + x1; y2 <= x0 + x1 + x2; y3 <= x0 + x1 + x2 + x3; y4 <= x0 + x1 + x2 + x3 + x4; y5 <= x0 + x1 + x2 + x3 + x4 + x5; end arch1; 2. Summat 2 Tee VHDL-kuvaus piiristä, joka laskee tehtävän 1 summat seuraavasti: y 0 = x 0, y 1 = y 0 + x 1, jne. Kellota piiri siten, että jokaisen välisumman ulostulossa on D-kiikku. Muista viivästää myös muita signaaleja D-kiikuilla. -- Pipeline: kiikut jokaisen summaimen jälkeen. -- Ulostulojen latenssiviiveet yhdenmukaistettu. architecture arch3 of Tablesum2 is -- Latenssiviivesignaalit signal s_x2_1, s_x3_1, s_x3_2, s_x4_1, s_x4_2, s_x4_3, s_x5_1, s_x5_2, s_x5_3, s_x5_4, s_x6_1, s_x6_2, s_x6_3, s_x6_4, s_x6_5 : std_logic_vector(bits-1 downto 0); signal s_y0_1, s_y0_2, s_y0_3, s_y0_4 : std_logic_vector(bits-1 downto 0); signal s_y1_1, s_y1_2, s_y1_3, s_y1_4 : std_logic_vector(bits-1 downto 0); signal s_y2_2, s_y2_3, s_y2_4 : std_logic_vector(bits-1 downto 0); signal s_y3_3, s_y3_4 : std_logic_vector(bits-1 downto 0); signal s_y4_4 : std_logic_vector(bits-1 downto 0); s_x2_1 <= (others => '0'); s_x3_1 <= (others => '0'); s_x3_2 <= (others => '0'); s_x4_1 <= (others => '0'); s_x4_2 <= (others => '0'); s_x4_3 <= (others => '0'); s_x5_1 <= (others => '0'); s_x5_2 <= (others => '0'); s_x5_3 <= (others => '0'); jako@uwasa.fi 3
s_x5_4 <= (others => '0'); s_y0_1 <= (others => '0'); s_y0_2 <= (others => '0'); s_y0_3 <= (others => '0'); s_y0_4 <= (others => '0'); y0 <= (others => '0'); s_y1_1 <= (others => '0'); s_y1_2 <= (others => '0'); s_y1_3 <= (others => '0'); s_y1_4 <= (others => '0'); y1 <= (others => '0'); s_y2_2 <= (others => '0'); s_y2_3 <= (others => '0'); s_y2_4 <= (others => '0'); y2 <= (others => '0'); s_y3_3 <= (others => '0'); s_y3_4 <= (others => '0'); y3 <= (others => '0'); s_y4_4 <= (others => '0'); y4 <= (others => '0'); y5 <= (others => '0'); -- 1. kerros s_x2_1 <= x2; s_x3_1 <= x3; s_x4_1 <= x4; s_x5_1 <= x5; s_y0_1 <= x0; s_y1_1 <= x0 + x1; -- 2. kerros s_x3_2 <= s_x3_1; s_x4_2 <= s_x4_1; s_x5_2 <= s_x5_1; s_y0_2 <= s_y0_1; s_y1_2 <= s_y1_1; s_y2_2 <= s_y1_1 + s_x2_1; -- 3. kerros s_x4_3 <= s_x4_2; s_x5_3 <= s_x5_2; s_y0_3 <= s_y0_2; s_y1_3 <= s_y1_2; s_y2_3 <= s_y2_2; s_y3_3 <= s_y2_2 + s_x3_2; -- 4. kerros s_x5_4 <= s_x5_3; s_y0_4 <= s_y0_3; jako@uwasa.fi 4
s_y1_4 <= s_y1_3; s_y2_4 <= s_y2_3; s_y3_4 <= s_y3_3; s_y4_4 <= s_y3_3 + s_x4_3; -- 5. kerros y0 <= s_y0_4; y1 <= s_y1_4; y2 <= s_y2_4; y3 <= s_y3_4; y4 <= s_y4_4; y5 <= s_y4_4 + s_x5_4; end arch3; 3. Summat 3 Tee VHDL-kuvaus piiristä, joka laskee tehtävän 1 summat käyttäen sopivaa pyramidirakennetta (tarvitaan kolme laskentakerrosta). Kellota piiri kerroksittain. Muista viivästää myös muita signaaleja D-kiikuilla. -- Rinnakkaissuutta hyödyntävä ratkaisu. -- Ulostulojen latenssiviiveet yhdenmukaistettu. architecture arch4 of Tablesum2 is -- Apusummat signal s_x23_1, s_x45_1, s_x45_2 : std_logic_vector(bits-1 downto 0); -- Latenssiviivesignaalit signal s_x2_1, s_x4_1, s_x4_2 : std_logic_vector(bits-1 downto 0); signal s_y0_1, s_y0_2 : std_logic_vector(bits-1 downto 0); signal s_y1_1, s_y1_2 : std_logic_vector(bits-1 downto 0); signal s_y2_2 : std_logic_vector(bits-1 downto 0); signal s_y3_2 : std_logic_vector(bits-1 downto 0); s_x23_1 <= (others => '0'); s_x45_1 <= (others => '0'); s_x45_2 <= (others => '0'); s_y0_1 <= (others => '0'); s_y0_2 <= (others => '0'); y0 <= (others => '0'); s_y1_1 <= (others => '0'); s_y1_2 <= (others => '0'); y1 <= (others => '0'); s_y2_2 <= (others => '0'); y2 <= (others => '0'); jako@uwasa.fi 5
s_y3_2 <= (others => '0'); y3 <= (others => '0'); y4 <= (others => '0'); y5 <= (others => '0'); -- 1. kerros s_x2_1 <= x2; s_x4_1 <= x4; s_x23_1 <= x2 + x3; s_x45_1 <= x4 + x5; s_y0_1 <= x0; s_y1_1 <= x0 + x1; -- 2. kerros s_x4_2 <= s_x4_1; s_x45_2 <= s_x45_1; s_y0_2 <= s_y0_1; s_y1_2 <= s_y1_1; s_y2_2 <= s_y1_1 + s_x2_1; s_y3_2 <= s_y1_1 + s_x23_1; -- 3. kerros y0 <= s_y0_2; y1 <= s_y1_2; y2 <= s_y2_2; y3 <= s_y3_2; y4 <= s_x4_2 + s_y3_2; y5 <= s_x45_2 + s_y3_2; end arch4; 4. Summat 4 Tee VHDL-kuvaus piiristä, joka laskee tehtävän 1 summat iteratiivisesti yhdellä summaimella. -- Iteratiivinen ratkaisu. Vastaa sekventiaalista ohjelmaa. architecture arch0 of Tablesum2 is signal s_y0, s_y1, s_y2, s_y3, s_y4, s_y5 : std_logic_vector(bits- 1 downto 0); variable i : Natural; i := 0; s_y0 <= (others => '0'); s_y1 <= (others => '0'); s_y2 <= (others => '0'); s_y3 <= (others => '0'); s_y4 <= (others => '0'); s_y5 <= (others => '0'); jako@uwasa.fi 6
case i is when 0 => s_y0 <= x0; s_y1 <= x0 + x1; when 1 => s_y2 <= s_y1 + x2; when 2 => s_y3 <= s_y2 + x3; when 3 => s_y4 <= s_y3 + x4; when 4 => s_y5 <= s_y4 + x5; when 5 => y0 <= s_y0; y1 <= s_y1; y2 <= s_y2; y3 <= s_y3; y4 <= s_y4; y5 <= s_y5; i := 0; when others => i := 0; end case; end arch0; jako@uwasa.fi 7