S Mikrosysteemien integrointi (2 op) Luento 03 PWB II

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1 S Mikrosysteemien integrointi (2 op) Luento 03 PWB II Contents: Multilayer PCBs HDI PCBs Integration of actives and passives Literature: C. Coombs, Printed circuit handbook R. Tummala, Introduction to System on Package, Chapter 7 Lasse Kemppainen, Monikerrospiirilevyn laatuun vaikuttavat tekijät, Kandidaatintyö 2010 Multilayer PCBs Patterned substrates (core boards) are stacked to form a multilayer structure In practice almost all the PCBs are multi-layered Signal layers are electrically connected with metallizated through holes or microvias Through hole Penetrates through the substrate Widely used technology in the PCB industry Hole diameter in mass production > mm Microvia Via diameter < 0.15 mm Used in build-up layers High Density Interconnection Ref: Oki Technical Review April 2010/Issue 216 Vol.77 No.1 1

2 Multilayer PCBs Monikerrospiirilevy valmistetaan kuparilla päällystetyistä levyistä, jotka koostuvat hartsista ja vahvikkeesta (laminaatti). Monikerrospiirilevyssä käytetään tavallisten laminaattien lisäksi niin sanottuja esiastelevyjä (pre-impregnated, prepreg). Esiastelevyn hartsi ei ole täysin kovettunutta, joten sitä kutsutaan myös B-vaiheen laminaatiksi. B-vaiheen hartsi sulaa ja jatkaa polymeroimista tietyssä lämpötilassa. Esiastelevyä käytetään monikerrospiirilevyssä kerrosten välissä liitoslevynä, joka sitoo piirilevykerrokset toisiinsa. Esiastelevy koostuu myös hartsista ja vahvikkeesta, mutta sitä ei ole päällystetty kuparilla. Valmiit esiastelevyt ja kuparilevyt leikataan sopivan kokoisiksi ja ladotaan haluttuun järjestykseen. Näitä kokonaisuuksia pinotaan päällekkäin metallilevyillä eroteltuna, jonka jälkeen ne prässätään. Prässäyksessä kuparilevyt kiinnittyvät esiastelevyyn paineen ja lämpötilan vaikutuksesta. Multilayer PCBs Double sided laminate Patterning (a subtractive process) Core board Copper foil Prepreg Laminating - Alignment - Heat & Pressure Patterning - Outer copper layer Drilling - Through holes - Metallization Buried via hole Plated through hole 2

3 Microvia technology Increasing functionality in electronic products Higher packaging density, more I/Os per. unit High Density Interconnection Microvia connects electrically HDI build-up layers Thickness of the dielectric layer ~10-35 m Microvia diameter ~ m ( < 150 µm) Depends of the application and manufacturing technology Aspect ratio 1:1 Microvias can be: Mechanically drilled Laser drilled CO 2 laser, UV-YAG laser, excimer laser, hybrid laser Photo defined Plasma etched Microvia technology Depending of the technology microvias are metallized: Chemical metallization Direct metallization Evaporation Sputtering Conductive polymers and pastes (ALIVH) The conductor pattern can be formed with subtractive, semi additive or fully additive process The planarity of the PCB is essential Microvias (and build-up layers) should not cause uneven surface 3

4 Plasma etched microvia Utilizes a gas plasma Usually a combination of oxygen and carbon tetrafluoride Mass formation process Number of vias does not affect to the production costs Manufacturing requires a hard mask E.g. copper foil Can not form via as small as photo or laser Isotropical etching Under etch (Large bowl-shaped vias) Requires vacuum Limited material choices Can not use glass-reinforced materials Photo defined microvia UV Light is transmitted through a glass mask The unreacted polymer is removed in the developing step All vias are fabricated simultaneously Number of vias doesn t affect the production cost Accurate alignment very important UV exposure The properties of the polymer are altered UV light Developing; The polymer is removed selectively with a wet chemical solution (negative polymer) BF-8000, BF-8500 : Hitachi Chemical Plating of microvias The vias are metallized to form electrical connection (e.g. with copper) Glass mask or Plastic film UV light 4

5 Photo defined microvia Sensitive fabrication process The resolution depends of the process and materials Polymers, UV light source, etc. Imaging techniques Contact Printing Mask and board are held in intimate contact Known technology & many suppliers Laser Projection Imaging (LPI) The pattern is formed using high power excimer laser to expose 16cm 2 area Laser Direct Imaging (LDI) Focused laser writes the pattern No mask required, slow, for prototypes Repeat-and-Step Imaging Board area is divided into several segments witch are imaged one at a time Image stitching errors Mechanically drilled microvia Low capital cost Existing equipment can be modified Not cots effective under 200 µm diameters Depth control important ± 5 µm possible Not practical in large volume mass production Hole diameter (inches) 5

6 Sequential process Laser defined microvia Vias are manufactured one at a time The number of vias effects the production costs Similar to mechanical drilling Material alternatives Compatible with conventional process Robust manufacturing process Not as high clean room requirements as photo defining process Laser -ablation Developing/cleaning; Plating of microvias The polymer is ablated to form a microvia Polymer remains are removed from the microvia The vias are metallized to form electrical connection (e.g. with copper) Laser beam CO 2 laser Laser defined microvia Most commonly used in the industry Over 90% absorption of radiation to dielectrics Good etching rate Fast & cost effecting State-of-the-art vias (diameter 100µm)/min Does not etch highly reflective material (e.g. copper) Necessary to etch a hole to the copper prior CO 2 laser ablation Thin (approx. 3µm) black oxidized copper can be etched with CO 2 Difficult to etch dielectrics with reinforcements Remove material thermally Melting, carbonization The spot size can be altered with a mask Minimum via approximately 75 µm Due to a long wavelength ( µm) 6

7 UV-YAG laser Laser defined microvia Can etch dielectric, copper, fillers Small spot size Order of 1 to 2 mils Slower than CO 2 laser when making big vias In order to manufacture bigger vias UV-YAG laser has to be moved in circles or spirals during ablation Photochemical or photothermal ablation no thermal damage occurs Excimer laser Expensive The best resolution but slow etching rate Hybrid laser UV-YAG laser is used to etch copper and CO 2 laser to etch dielectric High drilling rate, minimum via diameter 1 mil HDI substrates Microvias SBU layers Core board PTH Several different techniques to manufacture HDI build-up substrates ALIVH (developed by Matsushita) Any Layer Inner Via Hole SLC (developed by IBM) Surface Laminar Circuitry B 2 IT (developed by Toshiba) Buried Bump Interconnection Technology 7

8 ALIVH (Any Layer Inner Via Hole) Matsushita 1. Aramidi epoksiin reiät laserprosessilla 2. Reiät täytetään sähköä johtavalla pastalla 3. Kuparilaminaatti + resisti 4. Litografia 5. Laminointi B 2 it 1. Hopeanystytetty kuparikalvo, nystyt kartionmuotoisia 2. Laminointi prepreg-kalvoon 3-5. Monikerrosrakenteen valmistaminen 8

9 Printed Circuit Board (PCB) PCBs are used in electronic products to Form electrical connection between mounted components Thermal support Mechanical support PCB has been a non active component New advanced PCBs High Density Interconnection (HDI) Higher I/O count (e.g. CSP, Flip Chip) System On a Package PCBs with more functionality Passive component integration Resistors, capacitors, inductors Active component integration Chip Firs, Integrated Module Board Optical waveguide integration HDI build up layers Integrated passives Integrated actives Integrated actives challenges Reducing conductor line width and space High yield production Chip alignment Large panel sizes New materials Compatibility (e.g. CTE) Testing Modelling (e.g. thermo-mechanical) Known Good Die Problematic when bare chips are tested Rework processes Complicated, chip is embedded under interconnect structure Non-damaging laser-based processes (GE) 9

10 Chip First -process (by Fraunhofer-Institute) Cut holes into silicon Integrated actives techniques Plasma or wet etching, laser or jet cutting Lamination of Kapton film with an adhesive Chip insertion (optical alignment) Active area coplanar with the substrate Chips are fixed by filling up the gab with an adhesive, epoxy Removement of Kapton film Covering the embedded chips and the substrate with dielectric layer Photosensitive polymer imaging, vias Structuring the interconnect layer Sputtering (Al) Electroplating (Cu, Au) Integrated Module Board manufacturing Mechanically drilled trough holes Component alignment with FC - bonder Embedding active components with molding polymer Coating photo definable polymer over the substrate Photo defining the polymer Electroless metal deposition Coating a protective polymer layer over the substrate Attaching components to the module 10

11 Passiivien integrointi Eräs tapa hyödyntää piirilevyn pinta-alaa on resistiivisten, kapasitiivisten ja induktiivisten komponenttien hautaaminen piirilevyyn. Näin voidaan vähentää juoteliitosten määrää, jolloin kalustetun piirilevyn luotettavuus paranee. Piirilevyyn haudattuja vastuksia voidaan valmistaa päällystämällä sisäkerroksen kuparikalvo ohuella nikkelikalvolla ja poistamalla kupari sellaisista kohdista, joihin vastukset tulevat. Kondensaattoreita voidaan valmistaa asettamalla kahden kuparikalvon väliin hyvin ohut eriste. Tällä tavalla valmistetut kondensaattorit ovat erittäin laadukkaita. Induktiivisten komponenttien valmistuksessa ei tarvita erikoisia tekniikoita, vaan niitä voidaan valmistaa tekemällä tavalliseen johdinkuvioon spiraalimaisia johtimia. Passiivien integrointi laminoitavat vastuskalvot ohmega ply 11

12 Passiivien integrointi - laminoitavat vastuskalvot ohmega ply Valmistustoleranssit % Passiivien integrointi - vastukset Polymer Thick Film (PTF) vastukset Piirilevyn sisäkerrokseen määritetään vastukset print & etch prosessilla Johtimet musta-oksidoidaan Johtimen päät pinnoitetaan immersio hopealla Vastukset valmistetaan levyn pintaan silkkipainamalla Kovetetaan paistossa (230 C) Yleisin hiilimusta/fenoli pasta 12

13 Passiivien integrointi vastukset - trimmaus Yleensä integraalisten vastusten valmistusprosessin hajonta on kohtuullisen suurta ja vastusten trimmaus on välttämätöntä hidas ja kallis prosessivaihe 13